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CPU Memory Address Bus Widths
=============================
16-bit -> 64KB (65,536 bytes).
20-bit -> 1MB (1,048,576 bytes).
32-bit -> 4GB (4,294,967,296 bytes).


CPU Memory Access Models for 80386+
===================================
Real Mode Flat Model: 64K using 16-bit registers.
Real Mode Segmented Model: 64K segments along 1MB using 2 16-bit registers for
20-bit addresses.
Protected Mode Flat Model: 4GB using 32-bit registers.


16-bit General Purpose and Stack Pointer Registers
==================================================
Registers AX, BX, CX and DX can be divided into two separate 8-bit registers:
AX -> [AH/AL], BX -> [BH/BL], CX -> [CH/CL], DX -> [DH,DL].

?H = Higher 8-bit (MSB or Most Significant Byte).
?L = Lower 8-bit (LSB or Least Significant Byte).

Note: Only BX may contain a segment address offset and address memory data [].

AX (AH/AL): General purposes and math results.
BX (BH/BL): General purposes and indexing. Upper half concatenation with CX for a
32-bit count value.
CX (CH/CL): General purposes and counting. Byte count value of loaded file. Lower
16-bit half concatenation of BX and CX for a 32-bit count value.
DX (DH/DL): General purposes.

BP: General purposes, holding offsets and indexing.
SI: General purposes, source in data-movement operations.
DI: General purposes, destination in data-movement operations.

SP: Stack Pointer (points to next push in stack).


16-Bit Segment and Instruction Pointer Registers
================================================
Note: Available only in Real Mode Segmented Model, otherwise controlled by OS. May
be loaded from general purpose registers only, not immediate data or memory.
Can not be used for bitwise logical instructions (AND, OR, XOR, NOT).

DS = Data Segment address.
ES = Extra (spare) Segment address (386+ may include alphabetical clones FS and GS).
SS = Stack Segment address: Defines beginning of stack. SS:SP starts at the opposite
(top) end of allocated stack space and moves downwards to SS (see SP above).
CS = Code Segment address. CS:IP points to next instruction (see IP below).

IP = Instruction Pointer: Points to next machine instruction to be executed.


Real Mode Segmented Model and Addresses
=======================================
Simulates the 64K-limited Real Mode Flat Model by accessing up to 1MB of memory in
64K-sized (max.) segments. There are 65,536 segment starting slots spaced 16 bytes
apart (65,536 x 16 = 1,048,576). 2 16-bit registers are combined (segment:offset) to
define a 20-bit address along a 32-bit address bus as shown in examples below:

CS:IP (code segment:instruction pointer): address of next machine instruction.
CS:BX (code segment:general purpose): optional code segment address offset.
DS:SI (data segment:source index]: data segment address offset.
ES:DI (extra [spare] segment:destination index): spare segment address offset.
SS:SP (stack segment:stack pointer): address of next push in stack (LIFO buffer).
SS:BP (stack segment:base pointer): optional stack segment address offset.

0002:000D = 0:002D (decimal equivalent of 32 [2 x 16] + 13 or byte location 45).
073F:00FD (decimal equivalent of 29,680 + 253 or byte location 29,933).


Segment and General Purpose Register Assumptions
================================================
Instruction MOV assumes segment DS, except for SP and BP which assume segment SS:
MOV AX,[BX] assumes MOV AX,DS:[BX].
MOV [SI],DX assumes MOV DS:[SI],DX.
MOV [SP],DX assumes MOV SS:[SP],DX (may not be overridden).

Assumptions when executing string (contiguous sequence of bytes) instructions:
Source: DS:SI (Source Index, may not be overridden).
Destination: ES:DI (Destination Index, may not be overridden).
Length: CX (Counter), length of string.
Data coming from source string to destination string must pass through AX.

To override segment register assumptions:
MOV CS:[SI],AX overrides DS:[SI], MOV AX,ES:[BX] overrides AX,DS:[BX].


8-bit Flags Register and MS-DOS' DEBUG Symbology
================================================
Flag Name Set Clear

OF Overflow flag OV NV
DF Direction flag DN UP
IE Interrupt enable flag EI DI
SF Sign flag NG PL
ZF Zero flag ZR NZ
AF Auxiliary carry flag AC NA
PF Parity flag PE PO
CF Carry flag CY NC

E* = Extended 32-bit register for 32-bit Protected Mode Flat Model
(i.e. AX = EAX, SP = ESP, FLAGS = EFLAGS).


Illegal MOV Instructions Corrected
=========================================================================
MOV 17,1 Only one operand may be immediate data. MOV AX,17
MOV 17,BX Only the source operand may be immediate data. MOV BX,17
MOV CX,DH The operands must be the same size. MOV BL,DH
MOV [DI],[SI] Only one operand may be memory data. MOV [DI],SI
MOV DI,DX:[BX] DX is not a segment register. MOV DI,ES:[BX]
MOV ES,0B800 Seg. reg. may not be loaded from immed. data. MOV ES,DX
MOV DS,CS Only one operand may be a segment register. MOV DS,AX
MOV [AX],BP AX, CX and DX may not address memory data. MOV [BX],BP
MOV SI,[CS] Segment registers may not address memory data. MOV SI,CS


DOS and BIOS Software Interrupts
================================
0:0000-0:03FF: Interrupt vector table (256 entries x 4 bytes ea., 1,024 bytes).
INT 21H: DOS services dispatcher. AH: Service function. INT/(automatic IRET[urn])
pushes/pops next instruction address to/from Stack, also with CALL/RET(urn).


DOS Interrupt Call (09H Print String)
=====================================
mov DX,Msg ; Mem data ref without [] loads ADDRESS of string!
mov AH,09H ; Function 09H displays text (address from DX) to standard output.
int 21H ; INT 21H makes the call into DOS.

mov AX,04C00H ; Exits program (load 4CH [terminate process] into AH, 0 into AL).
int 21H ; Returns control to DOS, places AL into ERRORLEVEL DOS variable).


BIOS VIDEO Interrupt Call (10H), Service 2
==========================================
mov DX,[TextPos] ; TextPos contains X,Y (DL/DH) cursor position values.
call GotoXY ; Position cursor.
mov DX,Msg ; Load offset of Msg string into DX
call Write ; and display it.

GotoXY:
mov AH,02H ; Select VIDEO service 2: Position cursor.
mov BH,0 ; Stay with display page 0.
int 10H ; Call VIDEO.
ret ; Return to the caller.


BIOS VIDEO Interrupt Call (10H), Service 6
==========================================
Example 1:
mov CX,0422H ; Set upper-left corner to X=22H; Y=04H (CL/CH).
mov DX,093AH ; Set lower-right corner to X=3AH; Y=09H (DL/DH).
call ClrWin ; Call the ClrWin procedure, bypassing ClrScr.

Example 2:
mov CX,0422H ; Set upper-left corner to X=22H; Y=04H (CL/CH).
mov DX,093AH ; Set lower-right corner to X=3AH; Y=09H (DL/DH).
mov AL,01H ; Set to scroll window by one line.
call ScrlWin ; Call the ScrlWin procedure, bypassing ClrScr and ClrWin.

ClrScr:
mov CX,0 ; Upper left corner of full screen.
mov DX,LRXY ; Load lower-right XY coordinates (max. 79x24 [184FH]).
ClrWin:
mov AL,0 ; # of lines to scroll window (0 clears entire region).
ScrlWin:
mov BH,07H ; Specify "normal" attribute for blanked line(s).
VIDEO6:
mov AH,06H ; Select VIDEO service 6: Initialize/Scroll.
int 10H ; Call VIDEO.
ret ; Return to the caller.


Base-Indexed-Displacement Addressing
====================================
Addressing memory using three-part sum for serving two-level lookup tables such as:

MOV AX, [BX+DI+27]

BX (Base): Address of larger table.
DI (Index): Offset of sub-table within larger table.
27 (Displacement): Fixed distance between start of sub-table and addressed data.

Base register may be only BP or BX, index register may be only SI or DI.


IMUL (Integer Multiplication)
=============================
One operand must be in AL (for 8-bit) or AX (for 16-bit).
Product destination is AX (16-bit [+/- 32767]) or AX:DX (32-bit [+/- 2147483648])
with higher-order 16-bits in DX. Product larger than operands sets CF and OF.

==========

80x86 Integer Opcodes (alphabetical)
====================================
AAA - ASCII adjust after addition
AAD - ASCII adjust AX before division
AAM - ASCII adjust AX after multiplication
AAS - ASCII adjust AL after subtraction
ADC - Add with carry
ADD - Integer addition
AND - Logical AND
ARPL - Adjusted Requested Privilege Level of selector
BOUND - Array index bound check
BSF - Bit scan forward
BSR - Bit scan reverse
BSWAP - Byte swap
BT - Bit test
BTC - Bit test with compliment
BTR - Bit test with reset
BTS - Bit test and set
CALL - Call subroutine
CBW - Convert byte to word
CDQ - Convert double to quad
CLC - Clear carry
CLD - Clear direction flag
CLI - Clear interrupt flag
CLTS - Clear task switched flag
CMC - Complement carry flag
CMP - Compare
CMPS - Compare string (byte, word or doubleword)
CMPXCHG - Compare and exchange
CPUID - CPU identification
CWD - Convert word to doubleword
CWDE - Convert word to extended doubleword
DAA - Decimal adjust AL after addition
DAS - Decimal adjust AL after subtraction
DEC - Decrement
DIV - Unsigned divide
ENTER - Make stack frame for procedure parameters
ESC - Escape
HLT - Halt CPU
IDIV - Signed integer division
IMUL - Signed multiply
IN - Input byte or word from port
INC - Increment
INS - Input string from port (byte, word or doubleword)
INT - Interrupt
INTO - Interrupt on overflow
INVD - Invalidate data cache
INVLPG - Invalidate translation look-aside buffer (TLB) entry
IRET - Interrupt return
IRETD - Interrupt return
Jcc - Jump on condition code (Jump Instructions Table below)
JMP - Unconditional jump
LAHF - Load register flags into AH
LAR - Load access rights
LDS - Load far pointer
LEA - Load effective address
LEAVE - Restore stack for procedure exit
LES - Load far pointer
LFS - Load far pointer
LGDT - Load Global Descriptor Table
LGS - Load far pointer
LLDT - Load Local Descriptor Table
LOCK - Lock bus
LODS - Load string (byte, word or doubleword)
LOOP - Decrement CX and loop if CX not zero
LOOPE/LOOPZ - Loop while equal / loop while zero
LOOPNZ/LOOPNE - Loop while not zero / loop while not equal
LIDT - Load Interrupt Descriptor Table
LMSW - Load Machine Status Word
LSL - Load segment limit
LSS - Load far pointer
LTR - Load task register
MOV - Move data
MOVS - Move string (byte, word or doubleword)
MOVSX - Move with sign extend
MOVZX - Move with zero extend
MUL - Unsigned multiply
NEG - Two's complement negation
NOP - No operation
NOT - One's compliment negation (Logical NOT)
OR - Inclusive logical OR
OUT - Output data to port
OUTS - Output string to port (byte, word or doubleword)
POP - Pop word off stack
POPA/POPAD - Pop all registers onto stack
POPF/POPFD - Pop flags off stack
PUSH - Push word onto stack
PUSHA/PUSHAD - Push all registers onto stack
PUSHF/PUSHFD - Push flags onto stack
RCL - Rotate through carry left
RCR - Rotate through carry right
REP - Repeat string operation
REPE/REPZ - Repeat while equal / repeat while zero
REPNE/REPNZ - Repeat while not equal / repeat while not zero
RET/RETF - Return from procedure
ROL - Rotate left
ROR - Rotate right
SAHF - Store AH register into flags
SAL - Shift arithmetic left
SAR - Shift arithmetic right
SBB - Subtract with borrow / carry
SCAS - Scan string (byte, word or doubleword)
SETCC - Set byte on condition
SGDT - Store Global Descriptor Table
SHL - Shift logical left
SHLD - Double precision shift left
SHR - Shift logical right
SHRD - Double precision shift right
SIDT - Store Interrupt Descriptor Table
SLDT - Store Local Descriptor Table
SMSW - Store Machine Status Word
STC - Set carry flag
STD - Set direction flag
STI - Set interrupt flag (enable interrupts)
STOS [opt. B,W,D] - Store string (byte, word or doubleword)
STR - Store task register
SUB - Subtract
TEST - Test for bit pattern (logical compare)
UD2 - Undefined instruction
VERR - Verify read
VERW - Verify write
WAIT - Wait for coprocessor
WBINVD - Write-back and invalidate data cache
XADD - Exchange and add
XCHG - Exchange
XLAT/XLATB - Translate
XOR - Exclusive OR


Jump Instructions Table
=======================
Mnemonic Meaning Jump Condition
-------- ------- --------------
JA Jump if Above CF=0 and ZF=0
JAE Jump if Above or Equal CF=0
JB Jump if Below CF=1
JBE Jump if Below or Equal CF=1 or ZF=1
JC Jump if Carry CF=1
JCXZ Jump if CX Zero CX=0
JE Jump if Equal ZF=1
JG Jump if Greater (signed) ZF=0 and SF=OF
JGE Jump if Greater or Equal (signed) SF=OF
JL Jump if Less (signed) SF != OF
JLE Jump if Less or Equal (signed) ZF=1 or SF != OF
JMP Unconditional Jump unconditional
JNA Jump if Not Above CF=1 or ZF=1
JNAE Jump if Not Above or Equal CF=1
JNB Jump if Not Below CF=0
JNBE Jump if Not Below or Equal CF=0 and ZF=0
JN Jump if Not Carry CF=0
JNE Jump if Not Equal ZF=0
JNG Jump if Not Greater (signed) ZF=1 or SF != OF
JNGE Jump if Not Greater or Equal (signed) SF != OF
JNL Jump if Not Less (signed) SF=OF
JNLE Jump if Not Less or Equal (signed) ZF=0 and SF=OF
JNO Jump if Not Overflow (signed) OF=0
JNP Jump if No Parity PF=0
JNS Jump if Not Signed (signed) SF=0
JNZ Jump if Not Zero ZF=0
JO Jump if Overflow (signed) OF=1
JP Jump if Parity PF=1
JPE Jump if Parity Even PF=1
JPO Jump if Parity Odd PF=0
JS Jump if Signed (signed) SF=1
JZ Jump if Zero ZF=1